Datasheet

.text
.state32
.global __clearRegisters_
.asmfunc
__clearRegisters_:
mov r0, lr
mov r1, #0x0000
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mov r1, #0x11 ; FIQ Mode = 10001
msr cpsr, r1
msr spsr, r1
mov lr, r0
mov r8, #0x0000 ; Registers R8 to R12 are also
banked in FIQ mode
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mov r1, #0x13 ; SVC Mode = 10011
msr cpsr, r1
msr spsr, r1
mov lr, r0
mov r1, #0x17 ; ABT Mode = 10111
msr cpsr, r13
msr spsr, r13
mov lr, r0
mov r1, #0x12 ; IRQ Mode = 10010
msr cpsr, r13
msr spsr, r13
mov lr, r0
mov r1, #0x1B ; UDEF Mode = 11011
msr cpsr, r13
msr spsr, r13
mov lr, r0
mov r1, #0xDF ; System Mode = 11011111
msr cpsr, r13
msr spsr, r13
; Floating Point Co-Processor Initialization. FPU needs to be enabled first.
mrc p15, #0x00, r2, c1, c0, #0x02
orr r2, r2, #0xF00000
mcr p15, #0x00, r2, c1, c0, #0x02
mov r2, #0x40000000
fmxr fpexc, r2
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
fmdrr d11, r1, r1
fmdrr d12, r1, r1
fmdrr d13, r1, r1
fmdrr d14, r1, r1
fmdrr d15, r1, r1
bl $+4
bl $+4
bl $+4
bl $+4
bx r0
.endasmfunc
71
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
Submit Documentation Feedback
Product Folder Links: RM57L843
System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated