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13.2.1.2 Self-Test Mode
In self-test mode, the CCM-R5F checks itself for faults. During self-test, the compare error module output
signal is deactivated. Any fault detected inside the CCM-R5F will be flagged by ESM error “CCM-R5F -
self-test”.
In self-test mode, the CCM-R5F automatically generates test patterns to look for any hardware faults. If a
fault is detected, then a self-test error flag is set, a self-test error signal is asserted and sent to the ESM,
and the self-test is terminated immediately. If no fault is found during self-test, the self-test complete flag is
set. In both cases, the CCM-R5F CPU / VIM Output Compare Diagnostic remains in self-test mode after
the test has been terminated or completed, and the application needs to switch the CCM-R5F mode by
writing another key to the mode key register (MKEY1 or MKEY2 depending which diagnostic is selected
for self-test). During the self-test operation, the compare error signal output to the ESM is inactive
irrespective of the compare result.
There are two types of patterns generated by CCM-R5F during self-test mode:
1. Compare Match Test
2. Compare Mismatch Test
CCM-R5F first generates Compare Match Test patterns, followed by Compare Mismatch Test patterns.
Each test pattern is applied on both CPU signal inputs of the CCM-R5F’s compare block and clocked for
one cycle. The duration of self-test for CPU Output Compare Diagnostic is 4947 CPU clock cycles
(GCLK1) and 151 system peripheral clock cycles (VCLK) for VIM Output Compare Diagnostic.
NOTE: During self-test, both CPUs can execute normally, but the compare logic will not be checking
any CPU signals. Also during self-test, only the compare unit logic is tested and not the
memory-mapped register controls for the CCM-R5F. The self-test is not interruptible.
Self-test of all different diagnostics can be run at the same time.
13.2.1.2.1 Compare Match Test
During the Compare Match Test, there are four different test patterns generated to stimulate the CCM-
R5F. An identical vector is applied to both input ports at the same time expecting a compare match. These
patterns cause the self-test logic to exercise every CPU compare bus output signal in parallel. If the
compare unit produces a compare mismatch then the self-test error flag is set, the self-test error signal is
generated, and the Compare Match Test is terminated.
The four test patterns used for the Compare Match Test are:
• All 1s on both CPU / VIM signal ports
• All 0s on both CPU / VIM signal ports
• 0xAs on both CPU / VIM signal ports
• 0x5s on both CPU / VIM signal ports
These four test patterns will take four clock cycles to complete. Table 13-1 illustrates the sequence of
Compare Match Test.
Table 13-1. Compare Match Test Sequence
CPU 1 (Main CPU) Signal Position CPU 2 (Checker CPU) Signal Position
Cycle
n:8 7 6 5 4 3 2 1 0 n:8 7 6 5 4 3 2 1 0
1s 1 1 1 1 1 1 1 1 1s 1 1 1 1 1 1 1 1 0
0s 0 0 0 0 0 0 0 0 0s 0 0 0 0 0 0 0 0 1
0xA 1 0 1 0 1 0 1 0 0xA 1 0 1 0 1 0 1 0 2
0x5 0 1 0 1 0 1 0 1 0x5 0 1 0 1 0 1 0 1 3
482
SPNU562–May 2014
CPU Compare Module for Cortex
TM
-R5F (CCM-R5F)
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