Datasheet

www.ti.com EPC Control Registers
12.4.6 IP Interface FIFO Overflow Status Register (OVRFLWSTAT)
Figure 12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) (offset = 14h)
31 16
Reserved
R-0
15 5 4 3 2 1 0
Reserved OVFL4 OVFL3 OVFL2 OVFL1 OVFL0
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset
Table 12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved. Reads return 0.
4-0 OVFLn Correctable EPC-IP interface n FIFO overflow. Each bit corresponds to one correctable EPC-IP
interface FIFO status. If there is a FIFO overflow occurs, this bit is set. If any of these bits is set and the
FIFO overflow interrupt enable bit is set, EPC triggers FIFO overflow interrupt.
The number of implemented bits depends on the number of implemented EPC IP correctable address
ports. Unimplemented bits are reserved and are not writable. Reserved bits are read as 0.
Read:
0 No FIFO overflow.
1 FIFO overflow occurred.
Write in Privilege:
0 No effect.
1 Clear this flag bit.
12.4.7 CAM Index Available Status Register (CAMAVAILSTAT)
Figure 12-8. CAM Index Available Status Register (CAMAVAILSTAT) (offset = 18h)
31 16
Reserved
R-0
15 6 5 0
Reserved NUMCAMAVAIL
R-0 R-20h
LEGEND: R = Read only; -n = value after synchronous reset on system reset
Table 12-8. CAM Index Available Status Register (CAMAVAILSTAT) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reserved. Reads return 0.
5-0 NUMCAMAVAIL Number of current available CAM index. These bits indicate (binary encoded value) the number
of currently available CAM index.
0 Reserved
1h 1 CAM index available.
2h 2 CAM index available.
: :
20h 32 CAM index available.
475
SPNU562–May 2014 Error Profiling Controller (EPC)
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