Datasheet

RM57L843

SPNS215C –FEBRUARY 2014–REVISED JUNE 2016

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CCM-R5F also produces a signal to ESM GP1.92 to indicate its current status whether it is out of lockstep

or is in self-test mode. This ensures that any lock step fault is reported to the CPU.

6.5.4.1.2 Self-Test Mode

In self-test mode the CCM-R5F is checked for faults, by applying internally generated, series of test

patterns to look for any hardware faults inside the module. During self-test the compare error signal is

deactivated. If a fault on the CCM-R5F module is detected, an error is shown on the selftest_error pin.

6.5.4.1.3 Error Forcing Mode

In error forcing mode a test pattern is applied to the CPU and VIM related inputs of the compare logic to

force an error at the compare error signal of the compare unit. Error forcing mode is done separately for

VIM signal compare block and CPU signal compare block. For each block, this mode is enabled by writing

the key in corresponding block’s key register.

6.5.4.1.4 Self-Test Error Forcing Mode

In self-test error forcing mode an error is forced at the self-test error signal. The compare block is still

running in lockstep mode and the key is switched to lockstep after one clock cycle.

Table 6-7. CPU Compare Self-Test Cycles

MODE NUMBER OF GCLK CYCLES

Self-Test Mode 4947

Self-Test Error Forcing Mode 1

Error Forcing Mode 1

Table 6-8. VIM Compare Self-Test Cycles

MODE NUMBER OF VCLK CYCLES

Self-Test Mode 151

Self-Test Error Forcing Mode 1

Error Forcing Mode 1

6.5.4.2 Bus Inactivity Monitor

CCM-R5F also monitors the inputs to the interconnect coming from the checker Cortex-R5F core. The

input signals to the interconnect are compared against their default clamped values. The checker core

must not generate any bus transaction to the interconnect system as all bus transactions are carried out

through the main CPU core. If any signal value is different from its clamped value, an error signal is

generated. The error response in case of a detected transaction is sent to ESM.

In addition to bus monitoring the checker CPU core, the CCM-R5F will also monitor several other critical

signals from other masters residing in other power domains. This is to ensure an inadvertent bus

transaction from an unused power domain can be detected. To enable detection of unwanted transaction

from an unused master, the power domain in which the master to be monitored will need to be configured

in OFF power state through the PMM module.

6.5.4.3 CPU Registers Initialization

To avoid an erroneous CCM-R5F compare error, the application software must ensure that the CPU

registers of both CPUs are initialized with the same values before the registers are used, including

function calls where the register values are pushed onto the stack.

Example routine for CPU register initialization: