Datasheet

EPC Control Registers

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12.4.5 FIFO Full Status Register (FIFOFULLSTAT)

Figure 12-6. FIFO Full Status Register (FIFOFULLSTAT) (offset = 10h)

31 16

Reserved

R-0

15 5 4 3 2 1 0

Reserved FULL4 FULL3 FULL2 FULL1 FULL0

R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after asynchronous reset by power-on reset

Table 12-6. FIFO Full Status Register (FIFOFULLSTAT) Field Descriptions

Bit Field Value Description

31-5 Reserved 0 Reserved. Reads return 0.

4-0 FULLn FIFO interface n is full. If there is a FIFO full occurs on a particular interface, the corresponding bit is

set. If any of these bits is set and the CAM/FIFO full ena (enabled) bits are set, EPC triggers

cam_fifo_full_int.

The number of implemented bits depends on the number of implemented EPC IP correctable address

ports. Unimplemented bits are reserved and are not writable. Reserved bits are read as 0.

Read:

0 FIFO interface n is not full.

1 FIFO interface n full occurred.

Write in Privilege:

0 No effect.

1 Clear this flag bit.

474

Error Profiling Controller (EPC) SPNU562–May 2014

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