Datasheet

CPU Bus Compare
PD Inactivity
Monitor
VIM Bus Compare
Checker CPU
Inactivity Monitor
CPU1
(Main CPU)
CPU2
(Checker
CPU)
2 cycle delay
VIM1 VIM2
2 cycle delay
Inputs to CPU1
cpu2clk
cpu1clk
Outputs from CPU1 to
the system
Outputs from CPU2 to
the system
Safe values (values
that will force the
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to inactive states)
CCM-R5F
Compare errors
ESM
PDx PDy
69
RM57L843
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Figure 6-2. Dual Core Implementation
6.5.3 Duplicate Clock Tree After GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.
6.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety
CCM-R5F has two major functions. One is to compare the outputs of two Cortex-R5F processor cores and
the VIM modules. The second function is inactivity monitoring, to detect any faulted transaction initiated by
the checker core.
6.5.4.1 Signal Compare Operating Modes
The CCM-R5F module run in one of four operating modes - active compare lockstep, self-test, error
forcing, and self-test error forcing mode. To select an operating mode, a dedicated key must be written to
the key register. CPU compare block and VIM compare block have separate key registers to select their
operating modes. Status registers are also separate for these blocks.
6.5.4.1.1 Active Compare Lockstep Mode
In this mode the output signals of both CPUs and both VIMs are compared, and a difference in the outputs
is indicated by the compare_error terminal. For more details about CPU and VIM lockstep comparison,
refer to the device technical reference manual.