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NMPU Registers

11.4.9 MPU Type Register (MPUTYPE)

Figure 11-12. MPU Type Register (MPUTYPE) (offset = 2Ch)

31 16

Reserved

R-0

15 8 7 0

NUMREG Reserved

R-x R-0

LEGEND: R = Read only; -x = value is implementation defined

Table 11-12. MPU Type Register (MPUTYPE) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Reserved. Reads return 0.

15-8 NUMREG Number of MPU Regions. Indicates the number of implemented MPU regions.

0 Reserved

1h 1 MPU region is implemented.

2h 2 MPU regions are implemented.

3h 3 MPU regions are implemented.

4h 4 MPU regions are implemented.

5h 5 MPU regions are implemented.

6h 6 MPU regions are implemented.

7h 7 MPU regions are implemented.

8h 8 MPU regions are implemented.

All other values Reserved

7-0 Reserved 0 Reserved. Reads return 0.

459

SPNU562–May 2014 System Memory Protection Unit (NMPU)

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