Datasheet

www.ti.com NMPU Registers
11.4.1 MPU Revision ID Register (MPUREV)
Figure 11-4. MPU Revision ID Register (MPUREV) (offset = 00h)
31 30 29 28 27 16
SCHEME Reserved FUNC
R-1 R-0 R-A0Ch
15 11 10 8 7 6 5 0
RTL MAJOR CUSTOM MINOR
R-0 R-1 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-4. MPU Revision ID Register (MPUREV) Field Descriptions
Bit Field Value Description
31-30 SCHEME 1 Identification scheme.
29-28 Reserved 0 Reserved. Reads return 0.
27-16 FUNC A0Ch Indicates functionally equivalent module family. This value is dedicated to Hercules family from other
general Texas Instruments MCU or MPU family.
15-11 RTL 0 RTL version number
10-8 MAJOR 1 Major revision number
7-6 CUSTOM 0 Indicates device-specific implementation.
5-0 MINOR 0 Minor revision number
11.4.2 MPU Lock Register (MPULOCK)
Figure 11-5. MPU Lock Register (MPULOCK) (offset = 04h)
31 16
Reserved
R/-0
15 4 3 0
Reserved LOCK
R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-5. MPU Lock Register (MPULOCK) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved. Reads return 0.
3-0 LOCK MPU Register Lock Key. Lock feature prevents unintentional updates to MPU registers. Writes
to registers other than MPUERRSTAT is possible only when MPU is unlocked. This field is
updated only if the write data is 5h or Ah. Register writes are ignored for all other values of write
data.
A built-in correction logic detects single bit soft error on this field and corrects the value in the
next cycle. Functionality and register read data remain the same during the correction cycle.
Read: Returns current value of LOCK bits.
Write in Privilege:
5h Writes to other MPU registers are blocked
Ah Writes to other MPU registers are allowed
All other values Reserved. The bits remain unchanged.
453
SPNU562–May 2014 System Memory Protection Unit (NMPU)
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