Datasheet

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10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0])
This register is described in Figure 10-19 through Figure 10-22 and Table 10-17.
NOTE: This register gets reset to its default value with power-on or system reset assertion.
Figure 10-19. CORE2 Current MISR Register (CORE2_CURMISR3) [offset = 2Ch]
31 16
MISR[31:16]
R-0
15 0
MISR[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-20. CORE2 Current MISR Register (CORE2_CURMISR2) [offset = 30h]
31 16
MISR[63:48]
R-0
15 0
MISR[47:32]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-21. CORE2 Current MISR Register (CORE2_CURMISR1) [offset = 34h]
31 16
MISR[95:80]
R-0
15 0
MISR[79:64]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-22. CORE2 Current MISR Register (CORE2_CURMISR0) [offset = 38h]
31 16
MISR[127:112]
R-0
15 0
MISR[111:96]
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-17. CORE2 Current MISR Register (CORE2_CURMISRn) Field Descriptions
Bit Field Description
127-0 MISR MISR data from CORE2
This register contains the MISR data from the CORE2 for the most recent interval in case of segment 0l. This
value is compared with the GOLDEN MISR value copied from ROM.
435
SPNU562–May 2014 Self-Test Controller (STC) Module
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