Datasheet

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10.8.6 Self-Test Global Status Register (STCGSTAT)
This register is described in Figure 10-13 and Table 10-14.
NOTE: The two status bits can be cleared to their default values on a write of 1 to the bits.
Additionally when the STC_ENA key is written from a disabled state to enabled state, the two
status flags get cleared to their default values. This register gets reset to its default value
with power on reset assertion.
Figure 10-13. Self-Test Global Status Register (STCGSTAT) [offset = 14h]
31 16
Reserved
R-0
15 12 11 8 7 2 1 0
Reserved ST_ACTIVE Reserved TEST_FAIL TEST_DONE
R-0 R-5h R-0 R/W1CP-0 R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 10-14. Self-Test Global Status Register (STCGSTAT) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Read returns 0. Writes have no effect.
11-8 ST_ACTIVE This field indicates if the self-test is active.
Ah Self-test is active
All other values Self-test is not active
This will be set in the cycle after CORE_SEL is programmed. This will be reset once the STC
generated the CPU reset after completion of the self-test.
7-2 Reserved 0 Read returns 0. Writes have no effect.
1 TEST_FAIL Test Fail
0 Self-test run has not failed.
1 Self-test run has failed.
0 TEST_DONE Test Done
0 Not completed.
1 Self-test run completed.
The test done flag is set to a 1 for any of the following conditions:
1. When the STC run is complete without any failure
2. When a failure occurs on a STC run
3. When a timeout failure occurs
Reset is generated to the CPU on which the STC run is being performed when TEST_DONE
goes high (the test is completed).
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Self-Test Controller (STC) Module SPNU562–May 2014
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