Datasheet

www.ti.com STC Control Registers
10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1)
This register is described in Figure 10-11 and Table 10-12.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a
powerup reset or system reset, this register resets to all zeroes.
Figure 10-11. STC Current ROM Address Register (STCCADDR1) [offset = 0Ch]
31 0
ADDR
R-0
LEGEND: R = Read only; -n = value after nPORST (power on reset) or System reset
Table 10-12. STC Current ROM Address Register (STCCADDR1) Field Descriptions
Bit Field Description
31-0 ADDR Current ROM Address
This register reflects the current ROM address (address or micro code load) accessed during self-test
Segment0 -Core1 and other segments. This is the current value of the STC program counter.
10.8.5 STC Current Interval Count Register (STCCICR)
This register is described in Figure 10-12 and Table 10-13.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 or on a powerup reset, the current interval
counter resets to the default value.
Figure 10-12. STC Current Interval Count Register (STCCICR) [offset = 10h]
31 16
CORE2_ICOUNT
R-0
15 0
CORE1_ICOUNT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-13. STC Current Interval Count Register (STCCICR) Field Descriptions
Bit Field Description
31-16 CORE2_ICOUNT Interval Number
This specifies the last executed interval number for Core2 in case of self-test being run on Segement0
redundant cores.
15-0 CORE1_ICOUNT Interval Number
This specifies the last executed interval number for Core1 in case of self-test being run on Segment0 or
any other segments.
431
SPNU562–May 2014 Self-Test Controller (STC) Module
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