Datasheet

STC Control Registers www.ti.com
10.8 STC Control Registers
STC control registers are accessed through Peripheral Bus (VBUSP) interface. Read and write access in
8,16, and 32 bit are supported.
The base address for the control registers of STC1 is FFFF E600h. The base address for the control
registers of STC2 is FFFF 0800h.
NOTE: In suspend mode, all registers can be written irrespective of user or privilege mode and
reads will not clear the 'read-clear' bits.
Table 10-8. STC Control Registers
Offset Acronym Register Description Section
00h STCGCR0 STC Global Control Register 0 Section 10.8.1
04h STCGCR1 STC Global Control Register 1 Section 10.8.2
08h STCTPR Self-Test Run Timeout Counter Preload Register Section 10.8.3
0Ch STCCADDR1 STC Current ROM Address Register - CORE1 Section 10.8.4
10h STCCICR STC Current Interval Count Register Section 10.8.5
14h STCGSTAT Self-Test Global Status Register Section 10.8.6
18h STCFSTAT Self-Test Fail Status Register Section 10.8.7
1Ch CORE1_CURMISR3 CORE1 Current MISR Register Section 10.8.8
20h CORE1_CURMISR2 CORE2 Current MISR Register Section 10.8.8
24h CORE1_CURMISR1 CORE1 Current MISR Register Section 10.8.8
28h CORE1_CURMISR0 CORE1 Current MISR Register Section 10.8.8
2Ch CORE2_CURMISR3 CORE2 Current MISR Register Section 10.8.9
30h CORE2_CURMISR2 CORE2 Current MISR Register Section 10.8.9
34h CORE2_CURMISR1 CORE2 Current MISR Register Section 10.8.9
38h CORE2_CURMISR0 CORE2 Current MISR Register Section 10.8.9
3Ch STCSCSCR Signature Compare Self-Check Register Section 10.8.10
40h STCCADDR2 STC Current ROM Address Register - CORE2 Section 10.8.11
44h STCCLKDIV STC Clock Divider Register Section 10.8.12
48h STCSEGPLR STC Segment First Preload Register Section 10.8.13
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Self-Test Controller (STC) Module SPNU562–May 2014
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