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STC1 Segment 0 (CPU) Test Coverage and Duration

Table 10-2. STC1 Segment 0 Test Coverage and Duration (continued)

Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles)

44 90.57 71676 107 94.72 174303

45 90.67 73305 108 94.78 175932

46 90.77 74934 109 94.82 177561

47 90.89 76563 110 94.86 179190

48 91.00 78192 111 94.91 180819

49 91.08 79821 112 94.95 182448

50 91.17 81450 113 94.99 184077

51 91.26 83079 114 95.04 185706

52 91.35 84708 115 95.08 187335

53 91.42 86337 116 95.15 188964

54 91.52 87966 117 95.19 190593

55 91.63 89595 118 95.23 192222

56 91.73 91224 119 95.27 193851

57 91.81 92853 120 95.31 195480

58 91.89 94482 121 95.35 197109

59 91.97 96111 122 95.39 198738

60 92.05 97740 123 95.43 200367

61 92.11 99369 124 95.47 201996

62 92.17 100998 125 95.51 203625

Table 10-3 gives the typical STC execution times for 40 intervals and 125 intervals at different clock rates.

You can choose the number of intervals to be run based on the coverage needed and allowed time for

STC execution.

Table 10-3. Typical Execution Times for STC1 Segment 0

@ GCLK = 330 MHz @ GCLK = 300 MHz

Number of Intervals Coverage STCCLK = 110 MHz STCCLK = 100 MHz

40 >90% 592.4 uS 651.6 uS

125 >95% 1.8511 mS 2.036 mS

425

SPNU562–May 2014 Self-Test Controller (STC) Module

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