Datasheet

STC1 Segment 0 (CPU) Test Coverage and Duration www.ti.com
10.5 STC1 Segment 0 (CPU) Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in
Table 10-2.
Table 10-2. STC1 Segment 0 Test Coverage and Duration
Intervals Test Coverage Test Time (Cycles) Intervals Test Coverage Test Time (Cycles)
0 0 0 63 92.24 102627
1 56.85 1629 64 92.31 104256
2 64.19 3258 65 92.38 105885
3 68.76 4887 66 92.44 107514
4 71.99 6516 67 92.51 109143
5 75.00 8145 68 92.57 110772
6 76.61 9774 69 92.63 112401
7 78.08 11403 70 92.70 114030
8 79.20 13032 71 92.76 115659
9 80.18 14661 72 92.82 117288
10 81.03 16290 73 92.92 118917
11 81.90 17919 74 92.98 120546
12 82.58 19548 75 93.06 122175
13 83.24 21177 76 93.12 123804
14 83.73 22806 77 93.20 125433
15 84.15 24435 78 93.25 127062
16 84.52 26064 79 93.31 128691
17 84.90 27693 80 93.36 130320
18 85.26 29322 81 93.42 131949
19 85.68 30951 82 93.48 133578
20 86.05 32580 83 93.55 135207
21 86.40 34209 84 93.60 136836
22 86.68 35838 85 93.66 138465
23 86.94 37467 86 93.71 140094
24 87.21 39096 87 93.76 141723
25 87.48 40725 88 93.81 143352
26 87.74 42354 89 93.86 144981
27 87.98 43983 90 93.91 146610
28 88.18 45612 91 93.96 148239
29 88.38 47241 92 94.01 149868
30 88.56 48870 93 94.07 151497
31 88.75 50499 94 94.12 153126
32 88.93 52128 95 94.17 154755
33 89.10 53757 96 94.22 156384
34 89.23 55386 97 94.27 158013
35 89.41 57015 98 94.32 159642
36 89.55 58644 99 94.37 161271
37 89.70 60273 100 94.41 162900
38 89.83 61902 101 94.46 164529
39 89.96 63531 102 94.50 166158
40 90.10 65160 103 94.54 167787
41 90.23 66789 104 94.60 169416
42 90.33 68418 105 94.64 171045
43 90.43 70047 106 94.68 172674
424
Self-Test Controller (STC) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated