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10.4 Application Self-Test Flow
This section describes the STC module configuration and the application self-test flow that you should
follow for successful execution. The following two configurations must be part of the STC initialization
code:
• STC clock rate configuration, STC clock divider (STCCLKDIV) register is used to divide system clock
to generate STCCLK for each segment.
• Clear SYSESR register before triggering an STC test.
10.4.1 STC Module Configuration
• Configure the test interval count using STCGCR0[31:16] register. STC1, segment 0 supports a
maximum of 125 intervals, STC1 segment 1 supports a maximum of 3 and STC2 supports a maximum
of 57 intervals. The intervals within each group can be ran individually or sequentially at one time. If
the test intervals are run individually, the user software can specify to the self-test controller whether to
continue the run from the next interval or to restart from interval 0 using bit STCGCR0[0]. This bit gets
reset after the completion of the self-test run.
• Configure self-test run timeout counter preload register STCTPR. This register contains the total
number of VBUS clock cycles it will take before a self-test timeout error (TO_ERR) will be triggered
after the initiation of the self-test run.
• Configure Segment 0 for parallel or serial execution for each of the 2 elements to be tested (primary
and redundant logic).
• Enable self-test by writing the enable key to STCGCR1 register.
10.4.2 Context Saving - CPU
STC generates a CPU reset after completion of each test regardless of pass or fail. The STC test can be
ran at device startup or it can be divided into subsets of 1 or more intervals and executed during
application run time.
The STC test is a destructive test such that content within the element being tested may need to be
preserved.
If STC is run only on startup, the user software may note need to save the CPU content since the reset at
the completion of the test will be followed by normal device initializations/startup configuration. During
startup, the user code should check the STCGSTAT register for the self-test status before going to the
application software.
If STC is divided into intervals and ran during application run time, the user software must save the CPU
contents and reload them after each CPU reset caused by the completion of the STC test interval. The
check for STC status should bypass the STC run if the reset is caused by a completed test execution. The
STCGSTAT register should be checked for the self-test status before returning to the application software.
Following are some of the registers that are required to be backed up before and restored after self-test:
1. CPU core registers (all modes R0-R15, PC, CPSR)
2. CP15 System Control Coprocessor registers - MPU control and configuration registers, Auxiliary
Control Register used to Enable ECC, Fault Status Register etc.
3. CP13 Coprocessor Registers - FPU configuration registers, General Purpose Registers
4. Hardware Break Point and watch point registers like BVR, BSR, WVR, WSR etc.
For more information on the CPU reset, please refer to the Cortex-R5F Technical Reference Manual.
NOTE: Check all reset source flags in the SYSESR register after a CPU BIST execution. If a flag in
addition to CPU reset is set, clear the CPU reset flag and service the other reset sources
accordingly.
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SPNU562–May 2014 Self-Test Controller (STC) Module
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