Datasheet

PCR
ROM
Interface
ESM
ROM
Clock Controller
FSM
and
Sequence
Controller
COMP
BLK2
COMP
BLK1
Core_Reset
misr_out
misr_out
Global Clock
Controller
STC
STC REG
BLOCK
STC_BYPASS/
ATE Interface
VBUSP
Inteface
Test
Controller
DBIST
CNTRL2
CCM-R5F
DBIST
CNTRL1
CPU1
Cortex-R5F
(Bisted CORE)
CPU2
Cortex-R5F
(Bisted CORE)
General Description www.ti.com
Figure 10-5. STC1 - Segment 0 Redundant Core Architecture With Only CPU2 Selected
Modules highlighted in red will not be enabled for test while testing CORE2 only in a redundant system.
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Self-Test Controller (STC) Module SPNU562–May 2014
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