Datasheet

PCR
ROM
Interface
ESM
ROM
Clock Controller
FSM
and
Sequence
Controller
COMP
BLK2
COMP
BLK1
Core_Reset
misr_out
misr_out
Global Clock
Controller
STC
STC REG
BLOCK
STC_BYPASS/
ATE Interface
VBUSP
Inteface
Test
Controller
DBIST
CNTRL2
CCM-R5F
DBIST
CNTRL1
CPU1
Cortex-R5F
(Bisted CORE)
CPU2
(Bisted CORE)
Cortex-R5F
www.ti.com General Description
Figure 10-4. STC1 - Segment 0 Redundant Core Architecture With Only CPU1 Selected
Modules highlighted in red will not be enabled for test while testing CORE1 only in a redundant system.
417
SPNU562–May 2014 Self-Test Controller (STC) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated