Datasheet

PCR
ROM
Interface
ESM
ROM
Clock Controller
FSM
and
Sequence
Controller
COMP
BLK2
COMP
BLK1
Core_Reset
misr_out
misr_out
Global Clock
Controller
STC
STC REG
BLOCK
STC_BYPASS/
ATE Interface
VBUSP
Inteface
Test
Controller
DBIST
CNTRL2
Compare
DBIST
CNTRL1
CPU1
Cortex-R5F
(Bisted CORE)
CPU2
Cortex-R5F
(Bisted CORE)
www.ti.com General Description
Figure 10-2. STC1 - Segment 0 Redundant Core Architecture With CCM-R5F (Parallel Mode)
415
SPNU562–May 2014 Self-Test Controller (STC) Module
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