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PBIST Configuration Example www.ti.com
9.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups
This example explains the configurations for running March13 algorithm on all RAM groups defined in the
PBIST ROM.
1. Program the GCLK to PBIST ROM clock ratio to 1:4 in System Module.
MSTGCR[9:8] = 2
2. Enable PBIST Controller in System Module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in System Module.
MSTGCR[3:0] = 0xA
4. Wait for at least 64 VCLK cycles in a software loop.
5. Enable the Pbist internal clocks and ROM interface clock.
PACT = 0x3
6. Enable RAM Override.
OVER = 0x1
7. Select the Algorithms to be run (refer Table 2-6).
ALGO = 0x0000000C (select March13N for single-port and two-port RAMs)
8. Select both Algorithm and RAM information from on chip PBIST ROM.
ROM = 0x3
9. Configure PBIST to run in ROM Mode and kickoff PBIST test.
DLR = 0x14
10. Wait for PBIST test to complete by polling MSTDONE bit in System Module.
while (MSTDONE !=1)
11. Once self-test is completed, check the Fail Status registers FSRF0 and FSRF1.
In case there is a failure (FSRF0 or FSRF1 = 1):
(a) Read RAMT register that indicates the RGS and RDS values of the failure RAM.
(b) Read FSRC0 and FSRC1 registers that contain the failure count.
(c) Read FSRA0 and FSRA1 registers that contain the address of first failure.
(d) Read FSRDL0 and FSRDL1 registers that contain the failure data.
(e) Resume the Test if required using Program Control register (offset = 0x16C) STR = 2.
In case there is no failure (FSRF0 and FSRF1 = 0), the Memory self-test is completed.
(a) Disable the PBIST internal and ROM clocks.
PACT = 0
(b) Disable the PBIST self-test.
MSTGCR[3:0] = 0x5
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Programmable Built-In Self-Test (PBIST) Module SPNU562–May 2014
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