Datasheet

www.ti.com PBIST Control Registers
9.5.6 Fail Status Fail Registers (FSRF0 and FSRF1)
These registers indicate if a failure occurred during a memory self-test. Bit 0 gets set whenever a failure
occurs. FSRF0 indicates Port0 failures and FSRF1 indicates Port1 failures. The PBIST controller has
these two ports in order to optimize testing of single-port and dual-port RAMs. Figure 9-8 and Table 9-7
illustrate the FSRF0 register, while Figure 9-9 and Table 9-8 illustrate the FSRF1 register.
Figure 9-8. Fail Status Fail Register 0 (FSRF0) [offset = 0190h]
31 16
Reserved
R-0
15 1 0
Reserved FSRF0
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-7. Fail Status Fail Register 0 (FSRF0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Read returns 0. Writes have no effect.
0 FSRF0 Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in system
module.
0 No Failure Occurred
1 Indicates a failure on Port 0
Figure 9-9. Fail Status Fail Register 1 (FSRF1) [offset = 0194h]
31 16
Reserved
R-0
15 1 0
Reserved FSRF1
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-8. Fail Status Fail Register 1 (FSRF1) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Read returns 0. Writes have no effect.
0 FSRF1 Fail Status 1. This bit would be cleared by reset of the module using MSTGCR register in system
module.
0 No Failure Occurred
1 Indicates a failure on Port 1
401
SPNU562–May 2014 Programmable Built-In Self-Test (PBIST) Module
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