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PBIST Control Registers

9.5.4 PBIST ID Register

Functionality of the register is described in Figure 9-6 and Table 9-5.

Figure 9-6. PBIST ID Register [offset = 184h]

31 16

Reserved

R-0

15 8 7 0

Reserved PBIST ID

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-5. PBIST ID Register Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Reads return 0. Writes have no effect.

7-0 PBIST ID This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers.

399

SPNU562–May 2014 Programmable Built-In Self-Test (PBIST) Module

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