Datasheet

PBIST Control Registers

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9.5.3 PBIST Activate/ROM Clock Enable Register (PACT)

This is the first register that needs to be programmed to activate the PBIST controller. Bit [0] is used for

static clock gating, and unless a ‘1’ is written to this bit, all the internal PBIST clocks are shut off. Bit [1] is

for turning on the clock going to the instruction ROM. Figure 9-5 and Table 9-4 illustrate this register.

Figure 9-5. PBIST Activate/ROM Clock Enable Register (PACT) [offset = 0180h]

31 16

Reserved

R-0

15 2 1 0

Reserved PACT1 PACT0

R-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-4. PBIST Activate/ROM Clock Enable Register (PACT) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Read returns 0. Writes have no effect.

1 PACT1 PBIST Activate

0 Clock to on chip ROM is disabled

1 Normal PBIST operation for ROM based testing

0 PACT0 ROM Clock Enable Register

0 Disable internal PBIST clocks

1 Enable internal PBIST clocks

• PACT0

This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used

as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will

remain in an almost zero-power mode.

• PACT1

Setting this bit turns on the clock going to the instruction ROM.

NOTE: This register must be programmed to 3h during application self-test.

398

Programmable Built-In Self-Test (PBIST) Module SPNU562–May 2014

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