Datasheet

PBIST Control Registers

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9.5.1 RAM Configuration Register (RAMT)

This register is divided into following internal registers, none of which have a default value after reset.

Figure 9-3 and Table 9-2 illustrate this register.

This register provides the information regarding the memory being currently tested. In case of a PBIST

failure, the application can read this register to identify the RGS:RDS values for the memory that failed the

self-test.

Figure 9-3. RAM Configuration Register (RAMT) [offset = 0160h]

31 24 23 16

RGS RDS

R/W-X R/W-X

15 8 7 6 5 2 1 0

DWR SMS PLS RLS

R/W-X R/W-X R/W-X R/W-X

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-2. RAM Configuration Register (RAMT) Field Descriptions

Bit Field Description

31-24 RGS Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory.

23-16 RDS Return Data Select. Refer Table 2-5 for information on the RDS values for each memory.

15-8 DWR Data Width Register

7-6 SMS Sense Margin Select Register

5-2 PLS Pipeline Latency Select

1-0 RLS RAM Latency Select

396

Programmable Built-In Self-Test (PBIST) Module SPNU562–May 2014

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