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PBIST Control Registers

9.5 PBIST Control Registers

PBIST controller uses configuration registers for programming the algorithm and its execution. All the

configuration registers are memory mapped for access by the CPU through the Peripheral Bus interface.

The base address for the control registers is FFFF E400h.

NOTE: There is no watchdog functionality implemented in the PBIST controller. If a bad code is

executed, the PBIST will run forever. The PBIST controller does not guard against this

situation.

Registers are accessible only when the clock to PBIST controller is active. The clock is

activated by first writing 0x3 to PACT register.

Table 9-1. PBIST Registers

Offset Acronym Register Description Section

160h RAMT RAM Configuration Register Section 9.5.1

164h DLR Datalogger Register Section 9.5.2

180h PACT PBIST Activate/ROM Clock Enable Register Section 9.5.3

184h PBISTID PBIST ID Register Section 9.5.4

188h OVER Override Register Section 9.5.5

190h FSRF0 Fail Status Fail Register 0 Section 9.5.6

194h FSRF1 Fail Status Fail Register 1 Section 9.5.6

198h FSRC0 Fail Status Count Register 0 Section 9.5.7

19Ch FSRC1 Fail Status Count Register 1 Section 9.5.7

1A0h FSRA0 Fail Status Address Register 0 Section 9.5.8

1A4h FSRA1 Fail Status Address Register 1 Section 9.5.8

1A8h FSRDL0 Fail Status Data Register 0 Section 9.5.9

1B0h FSRDL1 Fail Status Data Register 1 Section 9.5.9

1C0h ROM ROM Mask Register Section 9.5.10

1C4h ALGO ROM Algorithm Mask Register Section 9.5.11

1C8h RINFOL RAM Info Mask Lower Register Section 9.5.12

1CCh RINFOU RAM Info Mask Upper Register Section 9.5.13

395

SPNU562–May 2014 Programmable Built-In Self-Test (PBIST) Module

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