Datasheet

t
f
t
r
V
CCIO
V
OH
V
OH
V
OL
V
OL
0
Output
62
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
for output buffer drive strength information on each signal.
Figure 5-3. CMOS-Level Outputs
Table 5-5. Timing Requirements for Outputs
(1)
MIN MAX UNIT
t
d(parallel_out)
Delay between low to high, or high to low transition of general-purpose output signals
that can be configured by an application in parallel, for example, all signals in a
GIOA port, or all N2HET1 signals, and so forth.
6 ns