Datasheet

Is system in
Yes
Setup memories, peripheral and clock tree like
clock by writing PACT=0x03
Select the RAM group and
algorithm using RAMINFO and
ALGO registers
Program OVER=0x00 for selftest without Override
Write ROM=0x03 to enable the
microcode load of the algorithm
and RAM info groups from the
on Chip ROM
Write 0x14 to DLR register to
configure PBIST in ROM mode
Is (MSTDONE =1)?
IS FSRF0=1 OR
PBIST Selftest Done
FSRF1=1 ?
Enable pbist clocks and ROM
Read RAMT reg for RGS/
Read FSRD and FSRA datalog
reg. for Fail data and address values
No
Yes
No
Yes
Wait for approximately N
vbus clocks.
Reset the PBIST controller by
writing MSTGCR=0x0A
Disable PBIST Test
Resume PBIST self test by writing
0x02 to the STR register
by writing MSTGCR=0x05
Disable pbist clocks and ROM
reset = 1?
clock by writing PACT = 0
or OVER = 1 for RAMINFO Override
No
RDS info
HCLK, VCLK peripheral and ROMCLK as required
for the PBIST test.
and start the Test
Enable PBIST controller by
by writing MSIENA = 0x01
www.ti.com PBIST Flow
9.3 PBIST Flow
Figure 9-1 illustrates the memory self-test flow.
Figure 9-2. PBIST Memory Self-Test Flow Diagram
391
SPNU562–May 2014 Programmable Built-In Self-Test (PBIST) Module
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