Datasheet

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8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST)
The RAMTEST register, shown in Figure 8-7 and described in Table 8-8, controls the test mode of the
L2RAMW Module.
Figure 8-7. L2RAMW Module Test Mode Control Register (RAMTEST) (offset = 30h)
31 16
Reserved
R-0
15 9 8 7 6 5 4 3 0
Reserved TRIGGER TEST MODE Reserved TEST ENABLE
R-0 R-0/WP-0 R/WP-0 R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 8-8. L2RAMW Module Test Mode Control Register (RAMTEST) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Read returns 0. Writes have no effect.
8 TRIGGER Test Trigger. This is an auto clear test trigger used to test the redundant address decode,
data merging mux, SECDED malfunction compare logic, and ECC checking logics. The
diagnostic test is executed when test mode is enabled and the test trigger is applied by
writing a 1 to this bit. The trigger is valid only if test mode is enabled, the correct mode is
configured in the TEST MODE field, and all diagnostic error bits in the RAMERRSTATUS
register are in the cleared state. The trigger bit is auto clear after the test and has to be
written again for a new test.
7-6 TEST MODE Test Mode. This field selects either equality or inequality testing schemes for redundant
address decoding and SECDED malfunction diagnostics.
If TEST MODE is set to 2h, equality check is done. The test stimulus stored in
ADDRTEST_VECT register is fed directly to both the channels of the comparator. If the
XOR of these two inputs is not zero then UERR interrupt is generated and ADDR COMP
LOGIC FAIL flag is set in RAMERRSTATUS register.
If TEST MODE is set to 1h, inequality check is done. The test stimulus stored in
ADDRTEST_VECT register is inverted and fed into one channel and the non-inverted
vector is fed into the other channel. If the XOR of these inputs is zero then the UERR
interrupt is generated and ADDR COMP LOGIC FAIL flag is set in RAMERRSTATUS
register.
5-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 TEST ENABLE Test Enable. This is a 4-bit key to enable the redundant address decode, SECDED
malfunction, data merging mux and ECC checking diagnostics. If the test scheme is
enabled then the compare logic uses the test vector inputs from the ADDRTEST_VECT,
DIAG_ECC, DIAG_DATA_VECTOR_L and DIAG_DATA_VECTOR_H registers. The
functional path comparison is disabled when test mode is enabled.
Ah Test mode is enabled.
All other values Test mode is disabled.
383
SPNU562–May 2014 Level 2 RAM (L2RAMW) Module
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