Datasheet

www.ti.com Control and Status Registers
Table 8-3. L2RAMW Module Control Register (RAMCTRL) Field Descriptions (continued)
Bit Field Value Description
27-24 ADDR PARITY OVERRIDE Address Parity Override. This field, when set to Ah, will invert the parity scheme
selected by the device global parity selection. The address parity checker would
then work on the inverted parity scheme. By default, the parity scheme is the
same as the global device parity scheme.
Ah Parity scheme is opposite to the device global parity scheme.
All other values Parity scheme is the same as the device global parity scheme.
23-21 Reserved 0 Read returns 0. Writes have no effect.
20 MSE MSE: Memory Scrubbing Enable. This bit enables or disables memory
scrubbing of single-bit errors on read operations.
Note: The ECC DETECT EN field in RAMCTRL register must be set to Ah
before enabling memory scrubbing, since memory scrubbing uses the
L2RAMW SECDED logic.
0 Memory scrubbing is disabled.
1 Memory scrubbing is enabled.
19-16 ADDR PARITY DISABLE Address/Control Bus Parity Detect Disable. This field, when set to 0xA, disables
the parity checking for the address and control bus. The parity checking is
enabled when this field is set to any other value.
Note: The application must ensure that PACE field in RAMERRSTATUS
register is cleared before enabling address/control bus parity checking.
Ah Address parity checking is disabled
All other values Address parity checking is enabled
15-13 Reserved 0 Read returns 0. Writes have no effect.
12 EEMMS EEMMS: Enable ESM notification (Parity, Redundant Address Decode,
SECDED malfunction) for write back during memory scrubbing.
0 ESM will not be signaled when an error occurs during memory scrubbing write
back
1 ESM will be signaled when an error occurs during memory scrubbing write back
11-9 Reserved 0 Read returns 0. Writes have no effect.
8 ECC WR EN ECC Memory Write Enable. This bit is provided to prevent accidental writes to
the ECC memory. A write access to the ECC memory is allowed only when the
ECC WR EN bit is set to 1. If this bit is cleared, then any writes to ECC memory
are ignored.
Note: Reads are allowed from the ECC memory regardless of the state of the
ECC WR EN.
0 ECC memory writes are disabled.
1 ECC memory writes are enabled.
7-5 Reserved 0 Read returns 0. Writes have no effect.
4 CPUWSC CPUWSC: CPU Write SERR Capture. By default, single bit error are not
signaled to ESM module. This bit allows the option to capture the status and
notify ESM.
Note: This feature is only applicable to CPU write data.
0 Disable single bit error status capture and ESM notification.
1 Enable single bit error status capture and ESM notification.
3-0 ECC DETECT EN ECC Detect Enable. This is a 4-bit key to enable the ECC detection feature in
the L2RAMW Module. Error detection, status updates, and data correction are
performed by the L2RAMW logic only if ECC detection is enabled. ECC
detection is enabled by default after reset.
Note: Disabling ECC on the L2RAMW module will disable ECC error
checking only for the ECC functions that the L2RAM handles (sub 64-bit
Write Operations). All other ECC handling is done by the R5F CPU. ECC
error checking cannot be disabled on the R5F CPU.
5h ECC detection is disabled.
All other values ECC detection is enabled.
377
SPNU562–May 2014 Level 2 RAM (L2RAMW) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated