Datasheet

V
CCIO
V
IH
V
IH
V
IL
0
Input
t
pw
V
IL
60
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report SPRA953
5.9 Thermal Resistance Characteristics for the BGA Package (ZWT)
Over operating free-air temperature range (unless otherwise noted)
(1)
°C / W
RΘ
JA
Junction-to-free air thermal resistance, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 14.3
RΘ
JB
Junction-to-board thermal resistance (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 5.49
RΘ
JC
Junction-to-case thermal resistance (2s0p PCB) 5.02
Ψ
JT
Junction-to-package top, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 0.29
Ψ
JB
Junction-to-board, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 6.41
(1) t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.
5.10 Timing and Switching Characteristics
5.10.1 Input Timings
Figure 5-2. TTL-Level Inputs
Table 5-3. Timing Requirements for Inputs
(1)
MIN MAX UNIT
t
pw
Input minimum pulse width t
c(VCLK)
+ 10
(2)
ns
t
in_slew
Time for input signal to go from V
IL
to V
IH
or from V
IH
to V
IL
1 ns