Datasheet

www.ti.com POM Control Registers
7.12.2 POM Revision ID Register (POMREV)
Figure 7-45. POM Revision ID Register (POMREV) (offset = 04h)
31 16
REVID
R-0108h
15 0
REVID
R-CA03h
LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up
Table 7-49. POM Revision ID Register (POMREV) Field Descriptions
Bit Field Value Description
31-0 REVID 0108CA03h Revision ID of POM
7.12.3 POM Flag Register (POMFLG)
This register conveys status bits that get set during POM accesses.
All these error status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect.
Figure 7-46. POM Flag Register (POMFLG) (offset = 0Ch)
31 16
Reserved
R-0
15 11 10 9 8
Reserved PERR_SRESP_IDLE PERR_PB PERR_PA
R-0 R/W1CP-u R/W1CP-u R/W1CP-u
7 0
Reserved
R-0
LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, cleared
on power up
Table 7-50. POM Flag Register (POMFLG) Field Descriptions
Bit Field Value Description
31-11 Reserved 0 Reads return 0. Writes have no effect.
10 PERR_SRESP_IDLE Idle response parity error on POM access
0 Idle response parity error on POM access has NOT occurred
1 Idle response parity error on POM access has occurred
9 PERR_PB Parity Error on POM access due to remapping request on PortB
0 Parity error on POM PortB remap request has NOT occurred
1 Parity error on POM PortB remap request has occurred
8 PERR_PA Parity Error on POM access due to remapping request on PortA
0 Parity error on POM PortA remap request has NOT occurred
1 Parity error on POM PortA remap request has occurred
7-0 Reserved 0 Reads return 0. Writes have no effect.
367
SPNU562–May 2014 F021 Level 2 Flash Module Controller (L2FMC)
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated