Datasheet

www.ti.com

Flash Control Registers

7.11.18 EEPROM Emulation Data MSW Register (FEMU_DMSW)

Figure 7-27. EEPROM Emulation Data MSW Register (FEMU_DMSW) (offset = 58h)

31 16

EMU_DMSW[63:48]

R/WP-0h

15 0

EMU_DMSW[47:32]

R/WP-0h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 7-30. EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions

Bit Field Description

31-0 EMU_DMSW This register can be written by the CPU in any mode.

This register is used in diagnostic mode 7 to XOR the upper 32b of the data being delivered to the bus

master.

7.11.19 EEPROM Emulation Data LSW Register (FEMU_DLSW)

Figure 7-28. EEPROM Emulation Data LSW Register (FEMU_DLSW) (offset = 5Ch)

31 16

EMU_DLSW[31:16]

R/WP-0h

15 0

EMU_DLSW[15:0]

R/WP-0h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 7-31. EEPROM Emulation Data LSW Register (FEMU_DLSW) Field Descriptions

Bit Field Description

31-0 EMU_DLSW This register can be written by the CPU in any mode.

This register is used in diagnostic mode 7 to XOR the lower 32b of the data being delivered to the bus

master.

355

SPNU562–May 2014 F021 Level 2 Flash Module Controller (L2FMC)

Submit Documentation Feedback