Datasheet

Flash Control Registers www.ti.com
7.11.11 Flash Bank Busy Register (FBBUSY)
Figure 7-20. Flash Bank Busy Register (FBBUSY) (offset = 38h)
31 16
Reserved
R-0
15 8 7 0
Reserved BUSY[7:0]
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 7-23. Flash Bank Busy Register (FBBUSY) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 BUSY Bank Busy. Each bit corresponds to a Flash bank.
0 The corresponding bank is not busy
1 The corresponding bank is busy with a state machine operation, or the bank is not implemented
7.11.12 Flash Bank Access Control Register (FBAC)
Figure 7-21. Flash Bank Access Control Register (FBAC) (offset = 3Ch)
31 24 23 16
Reserved OTPPROTDIS[7:0]
R-0 R/WP-0
15 8 7 0
BAGP VREADST
R/WP-0 R/WP-Fh
LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset
Table 7-24. Flash Bank Access Control Register (FBAC) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reads return 0. Writes have no effect.
23-16 OTPPROTDIS OTP Sector Protection Disable. Each bit corresponds to a Flash bank. This bit can be set only
when PROTL1DIS = 1 in the FBPROT register and in privilege mode.
0 Programming of the OTP sector is disabled.
1 Programming of the OTP sector is enabled.
15-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 VREADST 0-FFh VREAD Setup.
VREAD is generated by the Flash pump and used for Flash read operation. The bank power up
sequencing starts VREADST HCLK cycles after VREAD power supply becomes stable.
Note: There is not a programmable Bank Sleep counter and Standby counter register. The number
of clock cycles to transition from sleep to standby and standby to active is hardcoded in the Flash
wrapper design.
348
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
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