Datasheet

Flash Control Registers www.ti.com
7.11.7 Primary Address Tag Register (FPRIM_ADD_TAG)
This register is used to test the prefetch address tag registers. (see Section 7.8.2.1)
Figure 7-16. Primary Address Tag Register (FPRIM_ADD_TAG) (offset = 28h)
31 16
PRIM_ADD_TAG
RWP-0
15 5 4 0
PRIM_ADD_TAG Reserved
RWP-0 R-0
LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode;; -n = value after reset;
Table 7-19. Primary Address Tag Register (FPRIM_ADD)_TAG Field Descriptions
Bit Field Value Description
31-5 PRIM_ADD_TAG 0-7FF FFFFh Primary Address Tag Register
The primary address tag register selected by the DIAG_BUF_SEL bits in the
FDIAGCTRL register is memory-mapped here. This register can only be written in
privileged mode when diagnostic mode is enabled with DIAG_EN_KEY = 5h and
DIAGMODE = 5h in the FDIAGCTRL register. This register is not updated with new
flash data if DIAG_EN_KEY is not equal to 5h or DIAGMODE is 0 or 7h. Valid reads
can occur in any mode. The register clears when an address tag error is found and
when leaving DIAG_MODE 5.
4-0 Reserved 0 Reads return 0. Writes have no effect.
7.11.8 Duplicate Address Tag Register (FDUP_ADD_TAG)
This register is used to test the prefetch address tag registers. (see Section 7.8.2.1)
Figure 7-17. Duplicate Address Tag Register (FDUP_ADD_TAG) (offset = 2Ch)
31 16
DUP_ADD_TAG
RWP-0
15 5 4 0
DUP_ADD_TAG Reserved
RWP-0 R-0
LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode;; -n = value after reset;
Table 7-20. Duplicate Address Tag Register (FDUP_ADD)_TAG Field Descriptions
Bit Field Value Description
31-5 DUP_ADD_TAG 0-7FF FFFFh Duplicate Address Tag Register
The duplicate address tag register selected by the DIAG_BUF_SEL bits in the
FDIAGCTRL register is memory-mapped here. This register can only be written in
privileged mode when diagnostic mode is enabled with DIAG_EN_KEY = 5h and
DIAGMODE = 5h in the FDIAGCTRL register. This register is not updated with new
flash data if DIAG_EN_KEY is not equal to 5h or DIAGMODE is 0 or 7h. Valid reads
can occur in any mode. The register clears when an address tag error is found and
when leaving DIAG_MODE 5.
3-0 Reserved 0 Reads return 0. Writes have no effect.
346
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated