Datasheet

57
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
L2 flash is clocked by HCLK and is limited to maximum 150 MHz. The L2 flash can support zero data wait
state up to 45 MHz.