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7.11.5 Flash Global Error and Status Register (FEDAC_GBLSTATUS)
This register applies to global error and status flags in L2FMC.
All these status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect.
Figure 7-14. Flash Global Error and Status Register (FEDAC_GBLSTATUS) (offset = 1Ch)
31 24
Reserved FSM_DONE
R-0 RCP-0
23 16
Reserved
R-0
15 14 13 12 8
RCR_ERR IMPLICIT_COR_ IMPLICIT_UNC_ Reserved
ERR ERR
RCP-0 RCP-0 RCP-0 R-0
7 0
Reserved
R-0
LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, cleared
on power up
Table 7-17. Flash Global Error and Status Register (FEDAC_GBLSTATUS)
Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reads return 0. Writes have no effect.
24 FSM_DONE Flash State Machine Done
This bit is set to 1 when the flash state machine completes a program or erase operation.
This bit will generate an interrupt on VIM channel 61 if the FSM_EVT_EN bit of the
FSM_ST_MACHINE register is set. This bit must be cleared by writing a 1 to it in the
interrupt routine to clear the interrupt request.
23-16 Reserved 0 Reads return 0. Writes have no effect.
15 RCR_ERR Soft error in high integrity bits carrying implicit read data
0 No error detected in high integrity bits
1 Error detected in high integrity bits
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
14 IMPLICIT_COR_ERR Correctable error occurred during implicit reads
0 No single bit error is detected during implicit read
1 Single bit error is detected during implicit read
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
13 IMPLICIT_UNC_ERR Uncorrectable error occurred during implicit reads
0 No double bit error is detected during implicit read
1 Double bit error is detected during implicit read
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
12-0 Reserved 0 Reads return 0. Writes have no effect.
344
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
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