Datasheet

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7.11.4 Flash PortB Error and Status Register (FEDAC_PBSTATUS)
This register applies to accesses made to the main or EEPROM flash banks through PortB. .
All these error status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect.
Figure 7-13. Flash PortB Error and Status Register (FEDAC_PBSTATUS) (offset = 18h)
31 24
Reserved
R-0 R-0
23 16
Reserved
R-0
15 14 13 12 11 10 9 8
ACCTOUT MCMD_PAR_ Reserved ADD_TAG_ ADD_PAR_ Reserved
ERR ERR ERR
RCP-0 RCP-u R-0 RCP-u RCP-u R-0
7 0
Reserved
R-0
LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, cleared
on power up
Table 7-16. Flash PortB Error and Status Register (FEDAC_PBSTATUS)
Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15 ACCTOUT Severe error - internal switch timeout
0 L2FMC internal switch has NOT encountered a severe error (access timeout)
1 L2FMC internal switch has encountered a severe error (access timeout)
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
14 MCMD_PAR_ERR Parity Error in idle state. This bit is set when a parity error occurs during idle state of
PortB.
0 No idle state parity error is detected
1 Parity error is detected in idle state
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
13-12 Reserved 0 Reads return 0. Writes have no effect.
11 ADD_TAG_ERR PortB Address Tag Register Error Flag. This bit is set if the primary address tag has a hit
but the duplicate address tag does not match the primary address tag. This bit is
functional only when PortB prefetch mode is enabled (PFUENB=1).
0 Address Tag Register Error not detected on PortB
1 Address Tag Register Error detected on PortB
This error is routed to the ESM. Refer the device datasheet to find the group and channel
on which it is routed.
10 ADD_PAR_ERR Address Parity Error Flag.
0 No parity error was detected on the incoming access to the L2FMC PortB.
1 A parity error was detected on the incoming access to the L2FMC PortB. The address of
the erroneous access is not stored in L2FMC.
This error is routed to the ESM. Refer the device datasheet to find the specific group and
channel on which it is routed.
9-0 Reserved 0 Reads return 0. Writes have no effect.
343
SPNU562–May 2014 F021 Level 2 Flash Module Controller (L2FMC)
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