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Summary of L2FMC Errors www.ti.com
7.10 Summary of L2FMC Errors
Table 7-11. Errors in L2FMC
Does this Does this
Is a flag in
Scenario error cause a error go to Name of Flag
L2FMC set?
Bus Error? ESM?
FEDAC_PxSTATUS.
Access parity error/Internal parity errors Yes Yes Yes
ADD_PAR_ERR
FEDAC_PxSTATUS.
Port A/B Idle State parity error No Yes Yes
MCMD_PAR_ERR
FEDAC_PxSTATUS.
Address tag error Yes Yes Yes
ADD_TAG_ERR
Access to flash space beyond available
Yes No No -
size
Access to Flash while pump/bank are not
Yes No No -
active
FEDAC_PxSTATUS.
Flash Access time-out Yes Yes Yes
ACC_TOUT
Invalid access to L2FMC (for example,
Yes No No -
writes)
FEDAC_GBLSTATUS.
Single bit Error during Implicit Reads No Yes Yes
IMPLICIT_COR_ERR
FEDAC_GBLSTATUS.
Uncorrectable Error during Implicit Reads No Yes Yes
IMPLICIT_UNC_ERR
Access to bank while program/erase
Yes No No -
operations are ongoing on the same bank
Access to register address offsets
between 2C8h and 3FFh or 4B8h and Yes No No -
7FFh
Redirected access to POM received a bus
Yes No No -
error
Response of redirected access to POM
Yes No Yes POMFLG.PERR_Px
has access parity error
FEDAC_PxSTATUS.
POM Idle State parity error No Yes Yes
MCMD_PAR_ERR
Soft Errors in high integrity bits carrying FEDAC_GBLSTATUS.
No Yes Yes
Implicit read data RCR_ERR
338
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
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