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Emulation and SIL3 Diagnostic Modes www.ti.com
7.8.2.2 ECC Data Correction Diagnostic Mode 7: DIAGMODE = 7
Testing the error correction and ECC logic in the CPU involves corrupting the ECC value returned to the
CPU. By inverting one or more bits of the ECC, the CPU will detect errors in a selected data or ECC bit, or
in any possible value returned by the ECC.
To set an error for a particular bit use the syndrome, see Table 7-3. For instance, if you want to corrupt
data bit 62 then put the value 70h into the test register.
The method uses the FEMU_ECC register and the FEMU_DxSW registers to alter the ECC and data
respectively for one flash access port read. The values in the FEMU_ECC and FEMU_DxSW registers will
be XORed with the current ECC and data respectively to give a bad ECC or data value back to the bus
master. This will only occur for one read when the DIAG_MODE is 7, the DIAG_EN_KEY in the
FDIAGCTRL is 5 and the DIAG_TRIG is written with value '1' in FDIAGCTRL.
The sequence to do this test is:
1. Branch to a non-flash region to execute this sequence.
2. Set DIAG_MODE to 7 and DIAG_EN_KEY to 5. These fields are both present in the FDIAGCTRL
register.
3. Set desired values to XOR in the FEMU_ECC and FEMU_DxSW registers.
4. Set DIAG_TRIG to 1 in the FDIAGCTRL register.
5. Select the appropriate port in which the flip is desired using the DIAG_BUF_SEL field of the
FDIAGCTRL register. Only legal values are 0 for port A and 4 for port B.
6. Do a port A or B read to the desired address. The L2FMC will XOR the data and ECC with
FEMU_DxSW and FEMU_ECC respectively for this read before delivering it to the CPU. No further
reads are affected by this diagnostic.
7. The error routine of the bus master (for example, CPU) shall cause the address and erroneous bit to
be known. This should match with the bit flipped in step 3.
8. Repeat as necessary to test out various bits of data and ECC.
9. Set DIAG_MODE to 0 and the DIAG_EN_KEY to 0xA to completely disable this test.
NOTE: Make sure the address to be used for diagnostic is not already cached; otherwise, the read
will read from the cache memory instead of the flash.
7.8.3 Diagnostic Mode Summary
Table 7-10 gives a summary of the input registers needed for each mode, the possible registers that can
change, and the possible error bits in FEDACSTATUS that may set.
Table 7-10. Diagnostic Mode Summary
DIAG
MODE Name Inputs Possible Outputs Possible Error Bits Set Notes
5 Address Tag FPRIM_ADD_TAG ADD_TAG_ERR in This will cause ESM
FEDAC_PxSTATUS error. Please refer to the
register data manual to find
group and channel
FDUP_ADD_TAG
number.
FRAW_ADDR
6 Reserved
7 ECC test FEMU_ECC, Bus master will indicate None This will cause ESM
FEMU_DxSW data ECC single bit or error. Please refer to the
multi-bit error. data manual to find
group and channel
number.
336
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
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