Datasheet

www.ti.com Emulation and SIL3 Diagnostic Modes
7.8.2.1 Address Tag Register Test Mode 5: DIAGMODE = 5
There are six sets of address tag registers, two for PortA and four for PortB. Each set consists of a
primary and a duplicate address tag registers. Normally, these registers store the recently issued CPU
addresses during prefetch mode. To detect errors in these registers, the primary and duplicate address
tag registers are continuously compared to each other if the buffer is valid. If they are different, then an
address tag register error event is generated.
These registers are memory mapped. All primary address tag registers are memory mapped to one
address and likewise, all duplicate tag registers are mapped to another single address. During diagnostic
mode, each individual set can be selected via the 3-bit DIAG_BUF_SEL (Diagnostic buffer select) register.
User supplied values can be written into the selected set during a diagnostic mode. This diagnostic mode
uses the FRAW_ADDR register to supply the alternate address. When the DIAG_TRIG is set, the
FRAW_ADDR value is compared with the primary and the duplicate address tag registers. If the results of
the comparison are different, then the ADD_TAG_ERR (Address Tag Error) flag in FEDAC_PxSTATUS
will be set. Also, refer the device datasheet for the specific error channel which will be asserted in this
situation. This diagnostic mode uses the FRAW_ADDR register to supply the alternate address when
DIAG_TRIG is set. The sequence to do this test would be:
1. Branch to a non-flash region for executing this sequence. Ensure no requests from any bus master are
arriving at the port (A or B) that is being diagnosed.
2. Set DIAG_MODE to 5 and DIAG_EN_KEY to 5 in the FDIAGCTRL register.
3. Select the appropriate buffer to be diagnosed using the DIAG_BUF_SEL field of the FDIAGCTRL
register using the table in Section 7.11.22.
4. Set the FRAW_ADDR register to a certain arbitrary value 'A'. The lowest 5 bits should be set to 0.
5. Set the FPRIM_ADD_TAG register and the FDUP_ADD_TAG register in such a way that one of them
equals 'A' and the other one does not. The lowest 5 bits in both these writes should be set to 0.
6. Set the DIAG_TRIG bit in FDIAGCTRL register.
7. Now check the appropriate ADD_TAG_ERR bit based on the port being diagnosed. Ensure that it is '1'
implying successful operation of the compare logic.
8. Write '1' to the ADD_TAG_ERR bit to clear it.
9. Repeat for the different buffers.
10. At the end of the test set DIAG_MODE to 0 and DIAG_EN_KEY field to 0xA to completely disable the
test.
All address tags and buffer valid bits will be set to zero when leaving diag_mode 5.
NOTE: You should pre-load the registers with the test values with DIAG_TRIG = 0. After all test
values are written, the DIAG_TRIG should then be set high to validate the diagnostic result.
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SPNU562–May 2014 F021 Level 2 Flash Module Controller (L2FMC)
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