Datasheet

Data Waitstates
RAM
RWAIT Setting
Flash (Main Memory)
HCLK = 0MHz
HCLK = 0MHz
90MHz45MHz
0 1 3
0
135MHz
2
EWAIT Setting
HCLK = 0MHz
1 64
150MHz
150MHz
150MHz
EEPROM Flash (BUS2)
7
60MHz 90MHz 120MHz
45MHz
2
75MHz
3
8
135MHz105MHz
5
56
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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5.5 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 5-2. Clock Domain Timing Specifications
PARAMETER
TEST
CONDITIONS
MIN MAX UNIT
f
OSC
OSC - oscillator clock frequency using an external crystal 5 20 MHz
f
GCLK1
GCLK - R5F CPU clock frequency 330 MHz
f
GCLK2
GCLK - R5F CPU clock frequency 330 MHz
f
HCLK
HCLK - System clock frequency 150 MHz
f
VCLK
VCLK - Primary peripheral clock frequency 110 MHz
f
VCLK2
VCLK2 - Secondary peripheral clock frequency 110 MHz
f
VCLK3
VCLK3 - Secondary peripheral clock frequency 150 MHz
f
VCLKA1
VCLKA1 - Primary asynchronous peripheral clock frequency 110 MHz
f
VCLKA2
VCLKA2 - Secondary asynchronous peripheral clock frequency 110 MHz
f
VCLKA4
VCLKA4 - Secondary asynchronous peripheral clock frequency 110 MHz
f
RTICLK1
RTICLK1 - clock frequency f
VCLK
MHz
f
PROG/ERASE
System clock frequency - flash programming/erase f
HCLK
MHz
f
ECLK
External Clock 1 110 MHz
f
ETMCLKOUT
ETM trace clock output 55 MHz
f
ETMCLKIN
ETM trace clock input 110 MHz
f
EXTCLKIN1
External input clock 1 110 MHz
f
EXTCLKIN2
External input clock 2 110 MHz
Table 5-2 lists the maximum frequency of the CPU (GLKx), the level-2 memory (HCLK) and the peripheral
clocks (VCLKx). It is not always possible to run each clock at its maximum frequency as GCLK must be an
integral multiple of HCLK and HCLK must be an integral multiple of VCLKx. Depending on the system, the
optimum performance may be obtained by maximizing either the CPU frequency, the level-two RAM
interface, the level-two flash interface, or the peripherals.
5.6 Wait States Required - L2 Memories
Wait states are cycles the CPU must wait in order to retrieve data from the memories which have access
times longer than a CPU clock. Memory wrapper, SCR interconnect and the CPU itself may introduce
additional cycles of latency due to logic pipelining and synchronization. Therefore, the total latency cycles
as seen by the CPU can be more than the number of wait states to cover the memory access time.
Figure 5-1 shows only the number of programmable wait states needed for L2 flash memory at different
frequencies. The number of wait states is correlated to HCLK frequency. The clock ratio between CPU
clock (GCLKx) and HCLK can vary. Therefore, the total number of wait states in terms of GCLKx can be
obtained by taking the programmed wait states multiplied by the clock ratio.
There is no user programmable wait state for L2 SRAM access. L2 SRAM is clocked by HCLK and is
limited to maximum 150 MHz.
Figure 5-1. Wait States Scheme