Datasheet

Power On, Power Off Considerations www.ti.com
7.7 Power On, Power Off Considerations
7.7.1 Error Checking at Power On
As the device is coming out of the device reset sequence, the flash wrapper reads a configuration word
from the TI OTP section of bank zero. These are known as Implicit Reads. This is also readable from a
bus master at address 0xF0080140. During these reads ECC is enabled. Single bit errors are corrected
and uncorrectable errors will generate an error event. Accordingly, the IMPLICIT_COR_ERR or the
IMPLICIT_UNC_ERR bits in the FEDAC_GBLSTATUS register (offset=1ch) will get set. Refer the
datasheet to find the ESM group and channel number on which it is triggered.
7.7.2 Flash Integrity at Power Off
If power is lost during a programming or erase operation, a power-on reset must be asserted before the
core supply voltage drops below specification. The PORRST pin has a glitch filter that means that the
PORRST pin must be asserted low t
f(nPORRST)
(2 µs) before the core supply drops below Vcc
MIN
(1.14V). If
this requirement is met, then the bits being programmed when PORRST goes low are indeterminate,
however the other bits in the flash are not disturbed. Likewise, If this requirement is met, and PORRST is
asserted while erasing, the sector or sectors being erased will have indeterminate bits, however the other
sectors in the same bank, and the other banks will not be disturbed.
7.8 Emulation and SIL3 Diagnostic Modes
7.8.1 System Emulation
During emulation when the SUSPEND signal is high address tag and command parity error events are not
generated.
7.8.2 Diagnostic Mode
Flash wrapper can be put in diagnostic mode to verify various logic. There are multiple diagnostic modes
supported by the wrapper. A specific diagnostic mode is selected via the DIAGMODE control bits in the
diagnostic control register (FDIAGCTRL).
The diagnostic mode is only enabled by a 4-bit key stored in the DIAG_EN_KEY bits. Only
DIAG_EN_KEY = 5h enables any diagnostic mode and all diagnostic modes use the DIAG_TRIG to
initiate the action.
For all modes it is best to follow this sequence:
1. Write 5h to the DIAG_EN_KEY bits and set the desired DIAGMODE.
2. Set any data registers needed for this mode.
3. Write a 1 to the DIAG_TRIG bit to initiate the action and allow error to happen.
4. Write a Ah to DIAG_EN_KEY bits to exit the diagnostic modes.
Table 7-9. DIAGMODE Encoding
Mode DIAGMODE Bits Description
0 0 0 0 Diagnostic mode is disabled. Same as DIAG_EN_KEY not equal to 5h.
5 1 0 1 Address Tag Register test mode
7 1 1 1 ECC Data Correction
Others Other Combinations Reserved
334
F021 Level 2 Flash Module Controller (L2FMC) SPNU562–May 2014
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