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SECDED

7.4 SECDED

The Flash memory can be protected by Single Error Correction Double Error Detection (SECDED). This

protection is enabled by the SECDED circuit inside of the bus master.

7.4.1 SECDED Initialization

Flash error detection and correction is enabled at reset.

The ECC values for all of the flash memory space (flash banks 0 through 6) must be programmed into the

flash before the program/data can be read. This can be done by generating the correct values of the ECC

with an external tool such as nowECC or may be generated by the programming tool. The Cortex R5F

CPU may generate speculative fetches to any location within the flash memory space. A speculative fetch

to a location with invalid ECC, which is subsequently not used, will not create an abort, but will set the

ESM flags for a correctable or uncorrectable error. An uncorrectable error will unconditionally cause the

nERROR pin to toggle low. Therefore care must be taken to generate the correct ECC for the entire flash

space including the holes between sections and any unused or blank flash areas.

The Cortex R5F CPU does not generate speculative fetches into the address space of bank 7, the

EEPROM Emulation flash. Therefore, it is only necessary to initialize the ECC values of the locations

which will be intentionally read by the CPU or other bus masters.

7.4.2 ECC Encoding

Twenty-nine address lines are also included in the ECC calculation. A failure of a single address line

inside of the bank will result in an uncorrectable error at the bus master. The ECC encoding is shown in

Table 7-1.

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SPNU562–May 2014 F021 Level 2 Flash Module Controller (L2FMC)

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