Datasheet

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6.7.2 BOOT_REG: Boot Mode Register
Figure 6-11. BOOT_REG: Boot Mode Register (Offset = 20h)
31 16
Reserved
R-0
15 1 0
Reserved ENDIAN
R-0 R-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; R-D = Value read is determined by external configuration
Table 6-14. Boot Mode Register Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return zeros, writes have no effect.
0 ENDIAN Device endianness
0 Device is configured in little endian mode
1 Device is configured in big endian mode
6.7.3 KICK_REG0: Kicker Register 0
Figure 6-12. KICK_REG0: Kicker Register 0 (Offset = 38h)
31 16
KICK0
R/WP-0
15 0
KICK0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-15. Kicker Register 0 Field Descriptions
Bit Field Description
31-0 KICK0 Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU
write access to the PINMMRnn registers.
6.7.4 KICK_REG1: Kicker Register 1
Figure 6-13. KICK_REG1: Kicker Register 1 (Offset = 3Ch)
31 16
KICK1
R/WP-0
15 0
KICK1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 6-16. Kicker Register 1 Field Descriptions
Bit Field Description
31-0 KICK1 Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the
CPU write access to the PINMMRnn registers.
314
I/O Multiplexing and Control Module (IOMM) SPNU562–May 2014
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