Datasheet

53
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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Terminal Configuration and FunctionsCopyright © 2014–2016, Texas Instruments Incorporated
Table 4-28. Input Multiplexing (continued)
Address
Offset
Signal Name Default Terminal Terminal 1 Input
Multiplex Control
Alternate Terminal Terminal 2 Input
Multiplex Control
288h N2HET2[0] D6 PINMMR94[0] C1 PINMMR94[1]
N2HET2[1] D8 PINMMR94[8] D4 PINMMR94[9]
N2HET2[2] D7 PINMMR94[16] E1 PINMMR94[17]
N2HET2[3] E2 PINMMR94[24] D5 PINMMR94[25]
28Ch N2HET2[4] D13 PINMMR95[0] H3 PINMMR95[1]
N2HET2[5] D12 PINMMR95[8] D16 PINMMR95[9]
N2HET2[6] D11 PINMMR95[16] M1 PINMMR95[17]
N2HET2[7] N3 PINMMR95[24] N17 PINMMR95[25]
290h N2HET2[8] K16 PINMMR96[0] V2 PINMMR96[1]
N2HET2[9] L16 PINMMR96[8] K17 PINMMR96[9]
N2HET2[10] M16 PINMMR96[16] U1 PINMMR96[17]
N2HET2[11] N16 PINMMR96[24] C4 PINMMR96[25]
294h N2HET2[12] D3 PINMMR97[0] V6 PINMMR97[1]
N2HET2[13] D2 PINMMR97[8] C5 PINMMR97[9]
N2HET2[14] D1 PINMMR97[16] T1 PINMMR97[17]
N2HET2[15] K4 PINMMR97[24] C6 PINMMR97[25]
298h N2HET2[16] L4 PINMMR98[0] V7 PINMMR98[1]
N2HET2[18] N4 PINMMR98[8] E3 PINMMR98[9]
N2HET2[20] T5 PINMMR98[16] N2 PINMMR98[17]
N2HET2[22] T7 PINMMR98[24] N1 PINMMR98[25]
29Ch nTZ1_1 N19 PINMMR99[0] C3 PINMMR99[1]
nTZ1_2 F1 PINMMR99[8] B2 PINMMR99[9]
nTZ1_3 J3 PINMMR99[16] D19 PINMMR99[17]
4.2.2.2.1 Notes on Input Multiplexing
• The Terminal x Input Multiplex Control column in Table 4-28 lists the multiplexing control register and the bit that
must be set in order to select the terminal for providing the input signal to the system. For example, N2HET2[22]
can appears on two different terminals at terminal number T7 and N1. By default PINMMR98[24] is set and
PINMMR98[25] is cleared to select T7 for providing N2HET2[22] to the system. If the application chooses to use
N1 for providing N2HET2[22] then PINMMR98[24] must be cleared and PINMMR98[25] must be set.
• Base address of the IOMM module starts at 0xFFFF_1C00. Input mux control registers with the first register
PINMMR80 starts at the offset address 0x250 within the IOMM module.
4.2.2.2.2 General Rules for Multiplexing Control Registers
• The PINMMR control registers can only be written in privileged mode. A write in a nonprivileged mode will
generate an error response.
• If the application writes all 9’s to any PINMMR control register, then the default functions are selected for the
affected pads.
• Each byte in a PINMMR control register is used to select the functionality for a given pad. If the application sets
more than one bit within a byte for any pad, then the default function is selected for this pad.
• Several bits in the PINMMR control registers are reserved and are not used to enable any functions. If the
application sets only these bits and clears the other bits, then the default functions are selected for the affected
pads.