Datasheet

www.ti.com SDC MMR Registers
4.4.2 SDC Control Register (SDC_CONTROL)
Figure 4-3. SDC Control Register (SDC_STATUS) (offset = 04h)
31 16
Reserved
R-0
15 1 0
Reserved MASK_SOFT_RESET
R-0 RW-0
LEGEND: R = Read only; -n = value after reset
Table 4-7. SDC Control Register (SDC_CONTROL) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0 and writes have no effect.
0 MASK_SOFT_RESET This bit enables or disables the self-test sequence to be launched by by the SCM (SCR
Control Module) module. User should always keep this bit clear.
0 Enable SCM to launch self-test on the interconnect
1 Disable SCM to launch self-test on the interconnect
4.4.3 Error Generic Parity Register (ERR_GENERIC_PARITY)
Figure 4-4. Error Generic Parity Register (ERR_GENERIC_PARITY) (offset = 08h)
31 16
Reserved
R-0
15 6 5 0
Reserved ERR_GENERIC_PARITY
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 4-8. Error Generic Parity Register (ERR_GENERIC_PARITY) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reads return 0 and writes have no effect.
5-0 ERR_GENERIC_ Error related to parity mismatch in the higher order bits of the incoming address getting transmitted
PARITY across interconnect incorrectly. When set, each bit indicates the transaction processing block inside
the interconnect corresponding to the master is detected by the interconnect checker to have a
fault.
bit 0: PS_SCR_M master
bit 1: POM master
bit 2: DMA PortA master
bit 3: Reserved
bit 4: Cortex-R5F CPU master.
bit 5: ACP-M master
259
SPNU562–May 2014 Interconnect
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