Datasheet
CPU Interconnect Subsystem
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4.3.6 Interconnect Runtime Status
Both the CPU Interconnect Subsystem and the Peripheral Interconnect Subsystem will output its status on
each master and slave interface to the SCM indicating if the interface is currently active. The status are
captured in the SCMIASTAT register for the master interfaces and SCMTASTAT for the slave interfaces.
See Table 4-4 for the mapping between each interface to each bit field.
Table 4-4. SCM Register Bit Mapping
Register Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Remark
Each bit indicates
the transaction
processing block
inside the
SCMIAERR0 PS_SCR DMA CPU AXI-M CPU AXI-M interconnect
POM Reserved Reserved ACP-M
STAT _M Port A Read Write corresponding to the
master that is
detected by the
interconnect checker
to have a fault.
A timeout error
when the time the
request is issued by
the master until the
time the request is
accepted by the
slave has expired
A timeout error
when the time the
request is accepted
SCMIAERR1 PS_SCR DMA CPU AXI-M CPU AXI-M
POM Reserved Reserved ACP-M by the slave until the
STAT _M Port A Read Write
time the request is
responded by the
slave has expired
PS_SCR DMA CPU AXI-M CPU AXI-M Each bit indicates
POM Reserved Reserved ACP-M
_M Port A Read Write that there is still
pending transactions
Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
for the
SCMIASTAT
corresponding
master to be
DMA DAP/
HTUx Ethernet CPU PP-AXI Reserved
processed by the
PortB DMM
interconnect
L2 Flash L2 Flash PS_SCR Each bit indicates
L2 RAM EMIF Reserved CPU AXI-S ACP-S
Port B Port A _S that there is still
pending transactions
Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
SCMTASTAT for the
corresponding slave
to be processed by
PCR1 PCR2 PCR3 CRC1 CRC2 SDC MMR
the interconnect
256
Interconnect SPNU562–May 2014
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