Datasheet

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4.2.1 Accessing PCRx and CRCx Slave
System peripherals can be accessed via the PCR1 slave port. User peripherals can be accessed via
either the PCR2 or PCR3 slave ports. Refer to the datasheet for information on what peripherals are
available through each PCR. Peripheral Central Resource (PCR) is responsible to further decode the
slave address to select the desired peripheral.
There are two CRC modules implemented in the device. Both are direct slaves to the Peripheral
Interconnect Subsystem.
4.2.2 Accessing SDC MMR Port Slave
Safety Diagnostic Controller (SDC) MMR Port is a slave to the Peripheral Interconnect Subsystem to
access the safety diagnostic related control and status registers of the CPU Interconnect Subsystem.
Table 4-2 lists the CPU Interconnect Subsystem SDC register bit field mapping.
Table 4-2. CPU Interconnect Subsystem SDC Register Bit Field Mapping
Register Name Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Remark
Each bit indicates the
transaction processing block
inside the interconnect
corresponding to the master
ERR_GENERIC_ PS_SCR_ DMA_ CPU that is detected by the
POM Reserved ACP-M Reserved
PARITY M PORTA AXI-M interconnect checker to have a
fault.
Error related to parity
mismatch in the incoming
address
ERR_UNEXPECTED_ PS_SCR_ DMA_ CPU Error related to unexpected
POM Reserved ACP-M Reserved
TRANS M PORTA AXI-M transaction sent by the master
PS_SCR_ DMA_ CPU Error related to mismatch on
ERR_TRANS_ID POM Reserved ACP-M Reserved
M PORTA AXI-M the transaction ID
ERR_TRANS_ PS_SCR_ DMA_ CPU Error related to mismatch on
POM Reserved ACP-M Reserved
SIGNATURE M PORTA AXI-M the transaction signature
PS_SCR_ DMA_ CPU Error related to mismatch on
ERR_TRANS_TYPE POM Reserved ACP-M Reserved
M PORTA AXI-M the transaction type
PS_SCR_ DMA_ CPU Error related to mismatch on
ERR_USER_PARITY POM Reserved ACP-M Reserved
M PORTA AXI-M the parity
Each bit indicates the
transaction processing block
inside the interconnect
L2 Flash L2 Flash
SERR_UNEXPECTED_ L2 SRAM CPU corresponding to the slave that
Wrapper Wrapper EMIF Reserved ACP-S
MID Wrapper AXi-S is detected by the interconnect
Port A Port B
checker to have a fault.
Error related to mismatch on
the master ID
L2 Flash L2 Flash Error related to mismatch on
SERR_ADDR_ L2 SRAM CPU
Wrapper Wrapper EMIF Reserved ACP-S the most significant address
DECODE Wrapper AXi-S
Port A Port B bits
L2 Flash L2 Flash Error related to mismatch on
L2 SRAM CPU
SERR_USER_PARITY Wrapper Wrapper EMIF Reserved ACP-S the parity of the most
Wrapper AXi-S
Port A Port B significant address bits
4.2.3 Accessing Other Slaves via PS_SCR_S
In order for some of the masters connected to the Peripheral Interconnect Subsystem to access the slaves
such as L2 Flash and L2 SRAM in the CPU Interconnect Subsystem, their requests are first funneled into
the PS_SCR_S slave where it then becomes a master on the CPU Interconnect Subsystem as
PS_SCR_M. The request appearing on the PS_SCR_M is then decoded and routed to the intended slave
by the CPU Interconnect Subsystem.
252
Interconnect SPNU562–May 2014
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