Datasheet

HTU1 HTU2
Peripheral Interconnect Subsystem
DMA
PCR1
CPU Interconnect Subsystem
R5F
POM
DMM
DAP
PCR2 PCR3 CRC1 CRC2
EMAC
Flash
EMIFSRAM
A B
A
B
ACP
SDC MMR
PS_SCR_S
PS_SCR_M
ACP-M
ACP-S
SDC MMR Port
www.ti.com Overview
4.1 Overview
The interconnect is a bus matrix which interconnects the CPU cores, System DMA, other bus masters and
device specific slaves within the microcontroller. There are two interconnects in the microcontroller: the
CPU Interconnect Subsystem and the Peripheral Interconnect Subsystem. The interconnects direct the
access requests by the masters by providing decoding, arbitration, and routing of the requests to the
various slaves.
4.1.1 Block Diagram
Figure 4-1 is a block diagram of the Interconnects implemented in this family of microcontrollers.
Figure 4-1. Interconnect Block Diagram
4.2 Peripheral Interconnect Subsystem
There are masters and slaves connected to the Peripheral Interconnect Subsystem. Peripheral
Interconnect Subsystem is not a full cross-bar. Not all masters can access to all slaves. Table 4-1 lists the
implemented point to point connections between the masters and slaves.
Table 4-1. Bus Master / Slave Connectivity for Peripheral Interconnect Subsystem
Slaves on Peripheral Interconnect Subsystem
Master ID to SDC MMR
PCRx Masters CRC1 CRC2 PCR1 PCR2 PCR3 PS_SCR_S Port
0 CPU Yes Yes Yes Yes Yes No Yes
Read/Write
2 DMA Port B Yes Yes Yes Yes Yes No No
3 HTU1 No No No No No Yes No
4 HTU2 No No No No No Yes No
7 DMM Yes Yes Yes Yes Yes Yes No
9 DAP Yes Yes Yes Yes Yes Yes No
10 EMAC No No No Yes Yes Yes No
251
SPNU562–May 2014 Interconnect
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