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System and Peripheral Control Registers

2.5.3.35 Privileged Peripheral Frame n MasterID Protection Register_L/H (PPS[1-7]MSTID_L/H)

Figure 2-106. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H)

(offset = 408h-43Ch)

31 16

PPSn_QUAD3_MSTID or PPSn_QUAD1_MSTID

R/WP-FFFFh

15 0

PPSn_QUAD2_MSTID or PPSn_QUAD0_MSTID

R/WP-FFFFh

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-120. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H)

Field Descriptions

Bit Field Value Description

31-16 PPSn_QUAD3_MSTID or n: 1 to 7. L: quadrant0 and quadrant1. H: quadrant2 and quadrant3.

PPSn_QUAD1_MSTID MasterID filtering for Quadrant 3 of PPS[n] or Quadrant 1 of PPS[n]

0 Read: The corresponding master-id is not permitted to access the peripheral

Write: Disable the permission of the corresponding master to access the peripheral

1 Read: The corresponding master-id is permitted to access the peripheral

Write: Enable the permission of the corresponding master to access the peripheral

15-0 PPSn_QUAD2_MSTID or MasterID filtering for Quadrant 2 of PPS[n] or Quadrant 0 of PPS[n]

PPSn_QUAD0_MSTID

0 Read: The corresponding master-id is not permitted to access the peripheral

Write: Disable the permission of the corresponding master to access the peripheral

1 Read: The corresponding master-id is permitted to access the peripheral

Write: Enable the permission of the corresponding master to access the peripheral

231

SPNU562–May 2014 Architecture

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