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2.5.3.30 Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L)
Figure 2-101. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L)
(offset = 300h)
31 16
PS0_QUAD1_MSTID
R/WP-FFFFh
15 0
PS0_QUAD0_MSTID
R/WP-FFFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-115. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L)
Field Descriptions
Bit Field Value Description
31-16 PS0_QUAD1_MSTID MasterID filtering for Quadrant 1 of PS[0]. There are 16 bits for each quadrant in PS frame.
Each bit corresponds to a master-id value. For example, bit 0 corresponds to master-id 0
and bit 15 corresponds to master-id 15. These bits set the permission for maximum of 16
masters to address the peripheral mapped in each of the quadrant.
The following examples shows the usage of these register bits.
(a) If bits 15:0 are 1010_1010_1010_1010, then the peripheral that is mapped to Quadrant
0 of PS[0] can be addressed by Masters with Master-ID equals to 1,3,5,7,9,11,13,15.
(b) if bits 15:0 are 0000_0000_0000_0001, then the peripheral that is mapped to Quadrant
0 of PS[0] can only addressed by the master with the Master-ID equal to 0.
0 Read: The corresponding master-id is not permitted to access the peripheral mapped to this
quadrant
Write: Disable the permission of the corresponding master to access the peripheral mapped
to this quadrant
1 Read: The corresponding master-id is permitted to access the peripheral mapped to this
quadrant
Write: Enable the permission of the corresponding master to access the peripheral mapped
to this quadrant
15-0 PS0_QUAD0_MSTID MasterID filtering for Quadrant 0 of PS[0].
0 Read: The corresponding master-id is not permitted to access the peripheral mapped to this
quadrant
Write: Disable the permission of the corresponding master to access the peripheral mapped
to this quadrant
1 Read: The corresponding master-id is permitted to access the peripheral mapped to this
quadrant
Write: Enable the permission of the corresponding master to access the peripheral mapped
to this quadrant
226
Architecture SPNU562–May 2014
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